Publication Details
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Fortunato Frazzica, Toshio Yasue, Annachiara Spagnolo, David San Segundo Bello, Maarten De Bock, Jan Craninckx, Piet Wambacq
 

IEEE Sensors Journal

Contribution To Journal

Abstract 

This paper presents a 12 bit, 4.7 MS/s Digital Feed-Forward Incremental S? - Successive Approximation Register (DFF I- S? -SAR) Analog-to-Digital Converter (ADC) for column readout of image sensors. An input range detection phase and a new switching scheme for the DAC in the first stage allow reaching the desired 4 bit resolution of the I- S? stage with an Over Sampling Ratio (OSR) of 8. A second stage SAR converts the I- S? residue voltage resolving the 8 Least Significant Bits (LSBs). The ADC is integrated in a test chip with a Source Follower (SF) test unit that emulates a pixel array and is fabricated using 2-Poly-4-Metal 130 nm CMOS technology. The ADC operates under 3.3 V/1.2 V supply voltages, achieving a DNL of -0.43/0.62 12 bit LSBs, 356 µV rms noise, equivalent to 9.2 bit ENOB at a sampling frequency of 4.7 MS/s with an OSR of 8. The proposed ADC consumes 260.5 µW of power, yielding a Walden Figure-of-Merit 94 fJ/c.s.. The core area is 18400 µm2 .

Reference 
 
 
DOI scopus