A CMOS compatible III-v-on-300 mm SI technology for future high-speed communication systems: Challenges and possibilities
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AlN/Si interface engineering to mitigate RF losses in MOCVD grown GaN-on-Si substrates
Cardinael, P, Yadav, S, Hahn, H, Zhao, M, Banerjee, S, Esfeh, BK, Mauder, C, Sullivan, BO, Peralagu, U, Vohra, A, Langer, R, Collaert, N, Parvais, B & Raskin, J-P 2024 'AlN/Si interface engineering to mitigate RF losses in MOCVD grown GaN-on-Si substrates'.
An Adaptable In(Ga)P/Ga(Sb)As/Ga(In)As HBT Technology on 300 mm Si for RF Applications
Kumar, A, Yadav, S, Vais, A, Boccardi, G, Mols, Y, Alcotte, R, Parvais, B, Kunert, B & Collaert, N 2024, An Adaptable In(Ga)P/Ga(Sb)As/Ga(In)As HBT Technology on 300 mm Si for RF Applications. in 2024 IEEE/MTT-S International Microwave Symposium, IMS 2024. IEEE MTT-S International Microwave Symposium Digest, Institute of Electrical and Electronics Engineers Inc., pp. 940-943, 2024 IEEE/MTT-S International Microwave Symposium, IMS 2024, Washington, United States, 16/06/24. https://doi.org/10.1109/IMS40175.2024.10600299
First demonstration of III-V HBTs on 300 mm Si substrates using nano-ridge engineering
Vais, A, Alcotte, R, Ingels, M, Wambacq, P, Parvais, B, Langer, R, Kunert, B, Waldron, N, Collaert, N, Witters, L, Mols, Y, Hernandez, AS, Walke, A, Yu, H, Baryshnikova, M, Mannaert, G & Deshpande, V 2019, First demonstration of III-V HBTs on 300 mm Si substrates using nano-ridge engineering. in 2019 IEEE International Electron Devices Meeting, IEDM 2019., 8993539, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2019-December, Institute of Electrical and Electronics Engineers Inc., pp. 178-181, 65th Annual IEEE International Electron Devices Meeting, IEDM 2019, San Francisco, United States, 7/12/19. https://doi.org/10.1109/IEDM19573.2019.8993539
Design of a 28 GHz differential GaAs power amplifier with capacitive neutralization for 5G mmwave applications
Yan, D, Ingels, M, Mangraviti, G, Liu, Y, Parvais, B, Waldron, N, Collaert, N & Wambacq, P 2019, Design of a 28 GHz differential GaAs power amplifier with capacitive neutralization for 5G mmwave applications. in 17th IEEE International New Circuits and Systems Conference, NEWCAS 2019., 8961233, 17th IEEE International New Circuits and Systems Conference, NEWCAS 2019, Institute of Electrical and Electronics Engineers Inc., 17th IEEE International New Circuits and Systems Conference, NEWCAS 2019, Munich, Germany, 23/06/19. https://doi.org/10.1109/NEWCAS44328.2019.8961233
Device-, Circuit-Block-level evaluation of CFET in a 4 track library
Schuddinck, P, Zografos, O, Weckx, P, Matagne, P, Sarkar, S, Sherazi, Y, Baert, R, Jang, D, Yakimets, D, Gupta, A, Parvais, B, Ryckaert, J, Verkest, D & Mocuta, A 2019, Device-, Circuit-Block-level evaluation of CFET in a 4 track library. in 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers., 8776513, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2019-June, Institute of Electrical and Electronics Engineers Inc., pp. T204-T205, 39th Symposium on VLSI Technology, VLSI Technology 2019, Kyoto, Japan, 9/06/19. https://doi.org/10.23919/VLSIT.2019.8776513
Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling
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Purely analytical extraction of an improved nonlinear FinFET model including non-quasi-static effects
Crupi, G, Schreurs, DMMP, Caddemi, A, Angelov, I, Homayouni, M, Raffo, A, Vannini, G & Parvais, B 2009, 'Purely analytical extraction of an improved nonlinear FinFET model including non-quasi-static effects', Microelectronic Engineering, vol. 86, no. 11, pp. 2283-2289. https://doi.org/10.1016/j.mee.2009.04.006
Analog and RF circuits in 45 nm CMOS: planar bulk versus FinFET
Wambacq, P, Verbruggen, B, Scheir, K, Borremans, J, De Heyn, V, Van Der Plas, G, Mercha, A, Parvais, B, Subramanian, V, Jurzak, M, Decoutere, S & Donnay, S 2006, Analog and RF circuits in 45 nm CMOS: planar bulk versus FinFET. in Proceedings of ESSCIRC-ESSDIRC. Proceedings of ESSCIRC-ESSDIRC, pp. 54-57, Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet, Stockholm, Sweden, 21/09/09.
Analog and RF circuits in 45 nm CMOS and below: planar bulk versus FinFET
Wambacq, P, Verbruggen, B, Scheir, K, Borremans, J, De Heyn, V, Van Der Plas, G, Mercha, A, Parvais, B, Subramanian, V, Jurczak, M, Decoutere, S & Donnay, S 2006, Analog and RF circuits in 45 nm CMOS and below: planar bulk versus FinFET. in Proceedings of the 32nd European Solid-State Circuits Conference, Montreux, Switserland, September 19-21, 2006. pp. 54-57, Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet, Stockholm, Sweden, 21/09/09.
Junctionless gate-All-Around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells
Veloso, A, Parvais, B, Matagne, P, Simoen, E, Huynh-Bao, T, Paraschiv, V, Vecchio, E, Devriendt, K, Rosseel, E, Ercken, M, Chan, BT, Delvaux, C, Altamirano-Sanchez, E, Versluijs, JJ, Tao, Z, Suhard, S, Brus, S, Sibaja-Hernandez, A, Waldron, N, Lagrain, P, Richard, O, Bender, H, Chasin, A, Kaczer, B, Ivanov, T, Ramesh, S, De Meyer, K, Ryckaert, J, Collaert, N & Thean, A 2016, Junctionless gate-All-Around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells. in 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016., 7573409, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2016-September, Institute of Electrical and Electronics Engineers Inc., pp. 1-2, 36th IEEE Symposium on VLSI Technology, VLSI Technology 2016, Honolulu, United States, 13/06/16. https://doi.org/10.1109/VLSIT.2016.7573409
Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession
Chiarella, T, Witters, L, Mercha, A, Kerner, C, Rakowski, M, Ortolland, C, Ragnarsson, LA, Parvais, B, De Keersgieter, A, Kubicek, S, Redolfi, A, Vrancken, C, Brus, S, Lauwers, A, Absil, P, Biesemans, S & Hoffmann, T 2010, 'Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession', Solid-State Electronics, vol. 54, no. 9, pp. 855-860. https://doi.org/10.1016/j.sse.2010.04.010
Simple current and capacitance methods for bulk finFET height extraction and correlation to device variability
Chiarella, T, Parvais, B, Horiguchi, N, Togo, M, Kerner, C, Witters, L, Absil, P, Biesemans, S & Hoffmann, T 2011, Simple current and capacitance methods for bulk finFET height extraction and correlation to device variability. in 2011 IEEE International Conference on Microelectronic Test Structures - 24th ICMTS Conference Proceedings., 5976879, IEEE International Conference on Microelectronic Test Structures, pp. 158-161, 2011 24th IEEE International Conference on Microelectronic Test Structures, ICMTS 2011, Amsterdam, Netherlands, 4/04/11. https://doi.org/10.1109/ICMTS.2011.5976879