Metal-Organic Chemical Vapor Deposition Regrowth of Highly Doped n+ (In)GaN Source/Drain Layers for Radio Frequency Transistors
Banerjee, S, Peralagu, U, Alian, A, Zhao, M, Hahn, H, Minj, A, Vanhove, B, Vohra, A, Parvais, B, Langer, R & Collaert, N 2024, 'Metal-Organic Chemical Vapor Deposition Regrowth of Highly Doped n+ (In)GaN Source/Drain Layers for Radio Frequency Transistors', Physica Status Solidi (A) Applications and Materials Science, vol. 221, no. 21, 2400069. https://doi.org/10.1002/pssa.202400069
Power-performance trade-offs for Lateral NanoSheets on ultra-scaled standard cells
Garcia Bardon, M, Sherazi, Y, Jang, D, Yakimets, D, Schuddinck, P, Baert, R, Mertens, H, Mattii, L, Parvais, B, Mocuta, A & Verkest, D 2018, Power-performance trade-offs for Lateral NanoSheets on ultra-scaled standard cells. in 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018., 8510633, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2018-June, Institute of Electrical and Electronics Engineers Inc., pp. 143-144, 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018, Honolulu, United States, 18/06/18. https://doi.org/10.1109/VLSIT.2018.8510633
Scaling CMOS beyond Si FinFET: An analog/RF perspective
Parvais, B, Hellings, G, Simicic, M, Weckx, P, Mitard, J, Jang, D, Deshpande, V, Van Liempc, B, Veloso, A, Vandooren, A, Waldron, N, Wambacq, P, Collaert, N & Verkest, D 2018, Scaling CMOS beyond Si FinFET: An analog/RF perspective. in 2018 48th European Solid-State Device Research Conference, ESSDERC 2018., 8486857, European Solid-State Device Research Conference, vol. 2018-September, Editions Frontieres, Neuily sur Seine, France, pp. 158-161, 48th European Solid-State Device Research Conference, ESSDERC 2018, Dresden, Germany, 3/09/18. https://doi.org/10.1109/ESSDERC.2018.8486857
A 54-69.3 GHz Dual Band VCO with Differential Hybrid Coupler for Quadrature Generation
Shi, Q, Vaesen, K, Parvais, B, Mangraviti, G & Wambacq, P 2013, A 54-69.3 GHz Dual Band VCO with Differential Hybrid Coupler for Quadrature Generation. in 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC),. 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 325-328, Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian, Singapore, Malaysia, 11/11/13.
Low-voltage scaled 6T FinFET SRAM cells
Collaert, N, Von Arnim, K, Rooyackers, R, Vandeweyer, T, Mercha, A, Parvais, B, Witters, L, Nackaerts, A, Sanchez, EA, Demand, M, Hikavyy, A, Demuynck, S, Devriendt, K, Bauer, F, Ferain, I, Veloso, A, De Meyer, K, Biesemans, S & Jurczak, M 2010, Low-voltage scaled 6T FinFET SRAM cells. in Emerging Technologies and Circuits. Lecture Notes in Electrical Engineering, vol. 2021 LNEE, pp. 55-66, International Conference on Integrated Circuit Design and Technology, ICICDT 2008, Grenoble, France, 2/06/08. https://doi.org/10.1007/978-90-481-9379-0_4
Migrating from PLANAR to FinFET for further CMOS scaling: SOI or bulk?
Chiarella, T, Witters, L, Mercha, A, Kerner, C, Dittrich, R, Rakowski, M, Ortolland, C, Ragnarsson, LÃ…, Parvais, B, De Keersgieter, A, Kubicek, S, Redolfi, A, Rooyackers, R, Vrancken, C, Brus, S, Lauwers, A, Absil, P, Biesemans, S & Hoffmann, T 2009, Migrating from PLANAR to FinFET for further CMOS scaling: SOI or bulk? in ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference., 5325993, ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference, pp. 84-87, 35th European Solid-State Circuits Conference, ESSCIRC 2009, Athens, Greece, 14/09/09. https://doi.org/10.1109/ESSCIRC.2009.5325993
Migrating from Planar to FinFET for further CMOS scaling: SOI or bulk?
Chiarella, T, Witters, L, Mercha, A, Kerner, C, Dittrich, R, Rakowski, M, Ortolland, C, Ragnarsson, LÃ…, Parvais, B, De Keersgieter, A, Kubicek, S, Redolfi, A, Rooyackers, R, Vrancken, C, Brus, S, Lauwers, A, Absil, P, Biesemans, S & Hoffmann, T 2009, Migrating from Planar to FinFET for further CMOS scaling: SOI or bulk? in ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference., 5331587, ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference, pp. 85-88, 39th European Solid-State Device Research Conference, ESSDERC 2009, Athens, Greece, 14/09/09. https://doi.org/10.1109/ESSDERC.2009.5331587
Design of ultra-wideband low-noise amplifiers in 45-nm CMOS technology: Comparison between planar bulk and SOI FinFET devices
Ponton, D, Palestri, P, Esseni, D, Selmi, L, Tiebout, M, Parvais, B, Å iprak, D & Knoblinger, G 2009, 'Design of ultra-wideband low-noise amplifiers in 45-nm CMOS technology: Comparison between planar bulk and SOI FinFET devices', IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 5, pp. 920-932. https://doi.org/10.1109/TCSI.2009.2015178
Deep submicron CMOS for millimeter wave power applications
Ferndahl, M, Nemati, H, Parvais, B, Zirath, H & Decoutere, S 2008, 'Deep submicron CMOS for millimeter wave power applications', IEEE Microwave and Wireless Components Letters, vol. 18, no. 5, 4497806, pp. 329-331. https://doi.org/10.1109/LMWC.2008.922122
Determination and validation of new nonlinear FinFET model based on lookup tables
Crupi, G, Schreurs, DMMP, Xiao, D, Caddemi, A, Parvais, B, Mercha, A & Decoutere, S 2007, 'Determination and validation of new nonlinear FinFET model based on lookup tables', IEEE Microwave and Wireless Components Letters, vol. 17, no. 5, pp. 361-363. https://doi.org/10.1109/LMWC.2007.895711
Impact of fin width on digital and analog performances of n-FinFETs
Subramanian, V, Mercha, A, Parvais, B, Loo, J, Gustin, C, Dehan, M, Collaert, N, Jurczak, M, Groeseneken, G, Sansen, W & Decoutere, S 2007, 'Impact of fin width on digital and analog performances of n-FinFETs', Solid-State Electronics, vol. 51, no. 4 SPEC. ISS., pp. 551-559. https://doi.org/10.1016/j.sse.2007.02.003
Double-gate finFETs as a CMOS technology downscaling option: An RF perspective
Nuttinck, S, Parvais, B, Curatola, G & Mercha, A 2007, 'Double-gate finFETs as a CMOS technology downscaling option: An RF perspective', IEEE Transactions on Electron Devices, vol. 54, no. 2, pp. 279-283. https://doi.org/10.1109/TED.2006.888670
Stochastic matching properties of FinFETs
Gustin, C, Mercha, A, Loo, J, Subramanian, V, Parvais, B, Dehan, M & Decoutere, S 2006, 'Stochastic matching properties of FinFETs', IEEE Electron Device Letters, vol. 27, no. 10, pp. 846-848. https://doi.org/10.1109/LED.2006.882524
Modeling the SOI MOSFET nonlinearities: An empirical approach
Parvais, B & Siligaris, A 2006, Modeling the SOI MOSFET nonlinearities: An empirical approach. in Transistor Level Modeling For Analog/RF IC Design. Springer Netherlands, pp. 157-180. https://doi.org/10.1007/1-4020-4556-5_6
Suitability of FinFET technology for low-power mixed-signal applications
Parvais, B, Gustin, C, De Heyn, V, Loo, J, Dehan, M, Subramanian, V, Mercha, A, Collaert, N, Rooyackers, R, Jurczak, M, Wambacq, P & Decoutere, S 2006, Suitability of FinFET technology for low-power mixed-signal applications. in 2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06., 1669383, 2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06, IEEE Computer Society, Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference, Padova, Italy, 24/05/06. https://doi.org/10.1109/icicdt.2006.220796
Advanced process modules for (sub-) 45nm analog/RF CMOS - technology description and modeling challenges
Decoutere, S, Subramanian, V, Loo, J, Gustin, C, Parvais, B, Dehan, M & Mercha, A 2006, Advanced process modules for (sub-) 45nm analog/RF CMOS - technology description and modeling challenges. in Proceedings of the 1st European Microwave Integrated Circuits Conference, EuMIC 2006., 4057615, Proceedings of the 1st European Microwave Integrated Circuits Conference, EuMIC 2006, IEEE Computer Society, pp. 221-224, 1st European Microwave Integrated Circuits Conference, EuMIC 2006, Manchester, United Kingdom, 10/09/06. https://doi.org/10.1109/EMICC.2006.282792
MoM simulation of signal-to-noise patterns in infinite and finite receiving antenna arrays
Craeye, C, Parvais, B & Dardenne, X 2004, 'MoM simulation of signal-to-noise patterns in infinite and finite receiving antenna arrays', IEEE Transactions on Antennas and Propagation, vol. 52, no. 12, pp. 3245-3256. https://doi.org/10.1109/TAP.2004.836416
Impact of advanced process modules and device architectures on the matching performance of (sub-)45nm CMOS
Gustin, C, Mercha, A, Loo, J, Parvais, B, Subramaniant, V, Dehan, M, Veloso, A, Hoffmann, T, Leys, FE & Decoutere, S 2007, Impact of advanced process modules and device architectures on the matching performance of (sub-)45nm CMOS. in 2007 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA - Proceedings of Technical Papers., 4239536, International Symposium on VLSI Technology, Systems, and Applications, Proceedings, 2007 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA, Hsinchu, Taiwan, Province of China, 23/04/07. https://doi.org/10.1109/VTSA.2007.378968
Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay
Kubicek, S, Schram, T, Rohr, E, Paraschiv, V, Vos, R, Demand, M, Adelmann, C, Witters, T, Nyns, L, Delabie, A, Ragnarsson, LÃ…, Chiarella, T, Kerner, C, Mercha, A, Parvais, B, Aoulaiche, M, Ortolland, C, Yu, H, Veloso, A, Witters, L, Singanamalla, R, Kauerauf, T, Brus, S, Vrancken, C, Chang, VS, Chang, SZ, Mitsuhashi, R, Okuno, Y, Akheyar, A, Cho, HJ, Hooker, J, O'Sullivan, BJ, Van Elshocht, S, De Meyer, K, Jurczak, M, Absil, P, Biesemans, S & Hoffmann, T 2008, Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay. in Proceedings - CIS Workshops 2007, 2007 International Conference on Computational Intelligence and Security Workshops, CISW 2007., 4588590, Digest of Technical Papers - Symposium on VLSI Technology, pp. 130-131, 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT, Honolulu, HI, United States, 17/06/08. https://doi.org/10.1109/VLSIT.2008.4588590
Design of UWB LNA in 45nm CMOS technology: Planar Bulk vs. FinFET
Ponton, D, Palestri, P, Esseni, D, Selmi, L, Tiebout, M, Parvais, B & Knoblinger, G 2008, Design of UWB LNA in 45nm CMOS technology: Planar Bulk vs. FinFET. in 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008., 4542014, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 2701-2704, 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008, Seattle, WA, United States, 18/05/08. https://doi.org/10.1109/ISCAS.2008.4542014