Metal-Organic Chemical Vapor Deposition Regrowth of Highly Doped n+ (In)GaN Source/Drain Layers for Radio Frequency Transistors
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A CMOS compatible III-v-on-300 mm SI technology for future high-speed communication systems: Challenges and possibilities
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Charge Trapping and Emission during Bias Temperature Stressing of Schottky Gate GaN-on-Silicon HEMT Structures Targeting RF/mm Wave Power Amplifiers
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AlN/Si interface engineering to mitigate RF losses in MOCVD grown GaN-on-Si substrates
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Heterojunction bipolar transistors for sub-THz applications
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Effect of multiple conductions on basic parameters in linear and saturation regions for a MIS-HEMT from 450 K down to 200 K
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Large-Signal Characterisation and Analysis of AlN/GaN MISHEMTs on Si with a PAE > 62% at 28 GHz
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DC Reliability Study of high-? GaN-on-Si MOS-HEMT's for mm-Wave Power Amplifiers
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An Adaptable In(Ga)P/Ga(Sb)As/Ga(In)As HBT Technology on 300 mm Si for RF Applications
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Experimental study of MISHEMT from 450 K down to 200 K for analog applications
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From FinFET to Nanosheets and Beyond
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Advancements in IC Technologies: A look toward the future
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A snapshot review on metal–semiconductor contact exploration for 7-nm CMOS technology and beyond
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DC and RF Characterization of Nano-ridge HBT Technology Integrated on 300 mm Si Substrates
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Defect engineering for monolithic integration of III-V semiconductors on silicon substrates
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Analysis of Gate-Metal Resistance in CMOS-Compatible RF GaN HEMTs
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Low-Frequency Noise Investigation of GaN/AlGaN Metal–Oxide–Semiconductor High-Electron-Mobility Field-Effect Transistor With Different Gate Length and Orientation
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Deep-Level Transient Spectroscopy of GaAs Nanoridge Diodes Grown on Si Substrates
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3D sequential low temperature top tier devices using dopant activation with excimer laser anneal and strained silicon as performance boosters
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(Invited) Advanced Transistors for High Frequency Applications
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Exploring the DC reliability metrics for scaled GaN-on-Si devices targeted for RF/5G applications
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3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability
Vandooren, A, Franco, J, Parvais, B, Wu, Z, Witters, L, Walke, A, Li, W, Peng, L, Deshpande, V, Bufler, FM, Rassoul, N, Hellings, G, Jamieson, G, Inoue, F, Verbinnen, G, Devriendt, K, Teugels, L, Heylen, N, Vecchio, E, Zheng, T, Rosseel, E, Vanherle, W, Hikavyy, A, Chan, BT, Ritzenthaler, R, Besnard, G, Schwarzenbach, W, Gaudin, G, Radu, I, Nguyen, BY, Waldron, N, De Heyn, V, Mocuta, D & Collaert, N 2018, '3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability', IEEE Transactions on Electron Devices, vol. 65, no. 11, 8487028, pp. 5165-5171. https://doi.org/10.1109/TED.2018.2871265
3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability
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3D technologies for analog/RF applications
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The impact of sequential-3D integration on semiconductor scaling roadmap
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Vertical device architecture for 5nm and beyond: device & circuit implications
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Low-voltage scaled 6T FinFET SRAM cells
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A 10-bit current-steering FinFET D/A converter
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Impact of fin width on digital and analog performances of n-FinFETs
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Suitability of FinFET technology for low-power mixed-signal applications
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