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2024 
A CMOS compatible III-v-on-300 mm SI technology for future high-speed communication systems: Challenges and possibilities

Vais, A, Kumar, A, Boccardi, G, Yadav, S, Mols, Y, Alcotte, R, Vermeersch, B, Ingels, M, Peralagu, U, Neve, CR, Ghyselen, B, Parvais, B, Wambacq, P, Kunert, B & Collaert, N 2024, A CMOS compatible III-v-on-300 mm SI technology for future high-speed communication systems: Challenges and possibilities. in Key Enabling Technologies for Future Wireless, Wired, Optical and Satcom Applications. River Publishers, pp. 27-40. <https://www.taylorfrancis.com/chapters/oa-edit/10.1201/9781003587309-4/cmos-compatible-iii-300-mm-si-technology-future-high-speed-communication-systems-possibilities-vais-kumar-boccardi-yadav-mols-alcotte-vermeersch-ingels-peralagu-roda-neve-ghyselen-parvais-wambacq-kunert-collaert?context=ubx&refId=f3fb291e-2c77-409a-b9da-a1b3814ac758>

A D-band Power-Combined Stacked Common-Base Power Amplifier Achieving 20.9 dBm Psatand 24.3 % PAE in a 250-nm InP HBT Technology

Hemelhof, A, Park, S, Zhang, Y, Ingels, M, Gramegna, G, Vaesen, K, Yan, D & Wambacq, P 2024, A D-band Power-Combined Stacked Common-Base Power Amplifier Achieving 20.9 dBm Psatand 24.3 % PAE in a 250-nm InP HBT Technology. in 2024 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, BCICTS 2024. 2024 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, BCICTS 2024, Institute of Electrical and Electronics Engineers Inc., pp. 185-188, 2024 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, BCICTS 2024, Fort Lauderdale, United States, 27/10/24. https://doi.org/10.1109/BCICTS59662.2024.10745714

 
2021 
Design and Analysis of a 28 GHz T/R Front-End Module in 22-nm FD-SOI CMOS Technology

Tang, X, Liu, Y, Mangraviti, G, Zong, Z, Khalaf, K, Zhang, Y, Wu, W-M, Chen, S-H, Debaillie, B & Wambacq, P 2021, 'Design and Analysis of a 28 GHz T/R Front-End Module in 22-nm FD-SOI CMOS Technology', IEEE Transactions on Microwave Theory and Techniques, vol. 69, no. 6, 9366313, pp. 2841-2853. https://doi.org/10.1109/TMTT.2021.3059891

A 28-GHz SOI-CMOS Doherty Power Amplifier With a Compact Transformer-Based Output Combiner

Zong, Z, Tang, X, Khalaf, K, Yan, D, Mangraviti, G, Nguyen, J, Liu, Y & Wambacq, P 2021, 'A 28-GHz SOI-CMOS Doherty Power Amplifier With a Compact Transformer-Based Output Combiner', IEEE Transactions on Microwave Theory and Techniques, vol. 69, no. 6, 9380573, pp. 2795-2808. https://doi.org/10.1109/TMTT.2021.3064022

Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation

Renukaswamy, P, Markulic, N, Wambacq, P & Craninckx, J 2021, Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. in Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation., 9401690, 2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), Institute of Electrical and Electronics Engineers ( IEEE ), Daegu, Korea, pp. 1-5, 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, Republic of, 22/05/21. https://doi.org/10.1109/ISCAS51556.2021.9401690

DC and RF Characterization of Nano-ridge HBT Technology Integrated on 300 mm Si Substrates

Yadav, S, Vais, A, Elkashlan, RY, Witters, L, Vondkar, K, Mols, Y, Walke, A, Yu, H, Alcotte, R, Ingels, M, Wambacq, P, Langer, R, Kunert, B, Waldron, N, Parvais, B & Collaert, N 2021, DC and RF Characterization of Nano-ridge HBT Technology Integrated on 300 mm Si Substrates. in EuMIC 2020 - 2020 15th European Microwave Integrated Circuits Conference., 9337489, EuMIC 2020 - 2020 15th European Microwave Integrated Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 89-92, 15th European Microwave Integrated Circuits Conference, EuMIC 2020, Utrecht, Netherlands, 11/01/21.

 
2020 
Analysis of Gate-Metal Resistance in CMOS-Compatible RF GaN HEMTs

Elkashlan, RY, Rodriguez, R, Yadav, S, Khaled, A, Peralagu, U, Alian, A, Waldron, N, Zhao, M, Wambacq, P, Parvais, B & Collaert, N 2020, 'Analysis of Gate-Metal Resistance in CMOS-Compatible RF GaN HEMTs', IEEE Transactions on Electron Devices, vol. 67, no. 11, 9186848, pp. 4592-4596. https://doi.org/10.1109/TED.2020.3017467, https://doi.org/10.1109/TED.2020.3017467

A 10.56 Gbit/s,-27.8 dB EVM Polar Transmitter at 60 GHz in 28nm CMOS

Nguyen, JH-D, Khalaf, K, Brebels, S, Shrivas, M, Vaesen, K & Wambacq, P 2020, A 10.56 Gbit/s,-27.8 dB EVM Polar Transmitter at 60 GHz in 28nm CMOS. in 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)., 9218438, Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, vol. 2020-August, pp. 179-182, 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 4/08/20. https://doi.org/10.1109/RFIC49505.2020.9218438

Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication

Tsai, C-H, Zong, Z, Pepe, F, Mangraviti, G, Craninckx, J & Wambacq, P 2020, 'Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication', IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 55, no. 7, 9097192, pp. 1854-1863. https://doi.org/10.1109/JSSC.2020.2993717

Low 1/f(3) Noise Corner LC-VCO Design Using Flicker Noise Filtering Technique in 22nm FD-SOI

Zong, Z, Mangraviti, G & Wambacq, P 2020, 'Low 1/f(3) Noise Corner LC-VCO Design Using Flicker Noise Filtering Technique in 22nm FD-SOI', IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 5, 9014529, pp. 1469-1480. https://doi.org/10.1109/TCSI.2020.2970267

Design of D-Band Transformer-Based Gain-Boosting Class-AB Power Amplifiers in Silicon Technologies

Tang, X, Nguyen, J, Medra, A, Khalaf, K, Visweswaran, A, Debaillie, B & Wambacq, P 2020, 'Design of D-Band Transformer-Based Gain-Boosting Class-AB Power Amplifiers in Silicon Technologies', IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 5, 9004504, pp. 1447-1458. https://doi.org/10.1109/TCSI.2020.2974197

(Invited) Advanced Transistors for High Frequency Applications

Parvais, B, Peralagu, U, Vais, A, Alian, A, Witters, L, Mols, Y, Walke, A, Ingels, M, Yu, H, Putcha, V, Khaled, A, Rodriguez, R, Sibaja-Hernandez, A, Yadav, S, Elkashlan, R, Baryshnikova, M, Mannaert, G, Alcotte, R, Kunert, B, Simoen, E, Zhao, E, De Jaeger, B, Fleetwood, D, Langer, R, Zhao, M, Wambacq, P, Waldron, N & Collaert, N 2020, '(Invited) Advanced Transistors for High Frequency Applications', ECS Transactions, vol. 97, no. 27, pp. 27-38. https://doi.org/10.1149/09705.0027ecst

A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/μs Slope and 1.2GHz Chirp Bandwidth

Renukaswamy, P, Markulic, N, Park, S, Kankuppe Raghavendra Swamy, A, Shi, Q, Wambacq, P & Craninckx, J 2020, A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/μs Slope and 1.2GHz Chirp Bandwidth. in 2020 International Solid-State Circuits Conference., 17.7, Institute of Electrical and Electronics Engineers ( IEEE ), San Francisco, pp. 278-280, 2020 International Solid-State Circuits Conference, SAN FRANCISCO, Belgium, 16/02/20. https://doi.org/10.1109/ISSCC19947.2020.9063080

 
2019 
First demonstration of III-V HBTs on 300 mm Si substrates using nano-ridge engineering

Vais, A, Alcotte, R, Ingels, M, Wambacq, P, Parvais, B, Langer, R, Kunert, B, Waldron, N, Collaert, N, Witters, L, Mols, Y, Hernandez, AS, Walke, A, Yu, H, Baryshnikova, M, Mannaert, G & Deshpande, V 2019, First demonstration of III-V HBTs on 300 mm Si substrates using nano-ridge engineering. in 2019 IEEE International Electron Devices Meeting, IEDM 2019., 8993539, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2019-December, Institute of Electrical and Electronics Engineers Inc., pp. 178-181, 65th Annual IEEE International Electron Devices Meeting, IEDM 2019, San Francisco, United States, 7/12/19. https://doi.org/10.1109/IEDM19573.2019.8993539

Systematic Design of On-Chip Matching Networks for D-band Circuits

Nguyen, JH-D, Tang, X, Khalaf, K, Debaillie, B & Wambacq, P 2019, Systematic Design of On-Chip Matching Networks for D-band Circuits. in 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)., 8961221, IEEE, pp. 1-4, 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS), Munich, Germany, 23/06/19. https://doi.org/10.1109/NEWCAS44328.2019.8961221

A phased-array receiver for mm-wave applications

Wambacq, P & Szortyka, V Jun. 12 2019, A phased-array receiver for mm-wave applications, Patent No. EP2675080B.

Integrated 140 GHz FMCW Radar for Vital Sign Monitoring and Gesture Recognition

Vaesen, K, Visweswaran, A, Sinha, S, Bourdoux, A, van Liempd, B & Wambacq, P 2019, 'Integrated 140 GHz FMCW Radar for Vital Sign Monitoring and Gesture Recognition', Microwave journal (International ed.), vol. 62, no. 6, pp. 50-58.

Design of a 28 GHz differential GaAs power amplifier with capacitive neutralization for 5G mmwave applications

Yan, D, Ingels, M, Mangraviti, G, Liu, Y, Parvais, B, Waldron, N, Collaert, N & Wambacq, P 2019, Design of a 28 GHz differential GaAs power amplifier with capacitive neutralization for 5G mmwave applications. in 17th IEEE International New Circuits and Systems Conference, NEWCAS 2019., 8961233, 17th IEEE International New Circuits and Systems Conference, NEWCAS 2019, Institute of Electrical and Electronics Engineers Inc., 17th IEEE International New Circuits and Systems Conference, NEWCAS 2019, Munich, Germany, 23/06/19. https://doi.org/10.1109/NEWCAS44328.2019.8961233

A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With-41.3-dB EVM at 1024 QAM in 28-nm CMOS

Markulic, N, Renukaswamy, PT, Martens, E, van Liempd, B, Wambacq, P & Craninckx, J 2019, 'A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With-41.3-dB EVM at 1024 QAM in 28-nm CMOS', IEEE Journal of Solid-State Circuits, vol. 54, no. 4, 8629048, pp. 1059-1073. https://doi.org/10.1109/JSSC.2018.2886324

A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers

Lagos Benites, JL, Hershberg, B, Martens, E, Wambacq, P & Craninckx, J 2019, 'A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers', IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 54, no. 3, 8618444, pp. 646-658. https://doi.org/10.1109/JSSC.2018.2889680

 
2018 
A 60-GHz 8-Way Phased-Array Front-End With T/R Switching and Calibration-Free Beamsteering in 28-nm CMOS

Khalaf, K, Vaesen, K, Brebels, S, Mangraviti, G, Libois, M, Soens, C, Van Thillo, W & Wambacq, P 2018, 'A 60-GHz 8-Way Phased-Array Front-End With T/R Switching and Calibration-Free Beamsteering in 28-nm CMOS', IEEE Journal of Solid-State Circuits, vol. 53, no. 7, pp. 2001-2011. https://doi.org/10.1109/JSSC.2018.2822676

3D technologies for analog/RF applications

Vandooren, A, Parvais, B, Witters, L, Walke, A, Vais, A, Merckling, C, Lin, D, Waldron, N, Wambacq, P, Mocuta, D & Collaert, N 2018, 3D technologies for analog/RF applications. in 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. vol. 2018-March, 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, vol. 2018-March, Institute of Electrical and Electronics Engineers Inc., pp. 1-3, 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Burlingame, United States, 16/10/17. https://doi.org/10.1109/S3S.2017.8308746

 
2017 
A Single-Channel, 600Msps, 12bit, Ringamp-Based Pipelined ADC in 28nm CMOS

Lagos Benites, JL, Hershberg, B, Martens, E, Wambacq, P & Craninckx, J 2017, A Single-Channel, 600Msps, 12bit, Ringamp-Based Pipelined ADC in 28nm CMOS. in 2017 Symposium on VLSI Circuits, VLSI Circuits 2017., 8008561, Institute of Electrical and Electronics Engineers ( IEEE ), pp. C96-C97, 2017 Symposium on VLSI Circuits, 5/06/17. https://doi.org/10.23919/VLSIC.2017.8008561

A fully-integrated method for RTN parameter extraction

Simicic, M, Morrison, S, Parvais, B, Weckx, P, Kaczer, B, Sawada, K, Ammo, H, Yamakawa, S, Nomoto, K, Ohno, M, Linten, D, Verkest, D, Wambacq, P, Groeseneken, G & Gielen, G 2017, A fully-integrated method for RTN parameter extraction. in Digest of Technical Papers - Symposium on VLSI Technology. Digest of Technical Papers - Symposium on VLSI Technology, Institute of Electrical and Electronics Engineers Inc., pp. T132-T133, Symposium on VLSI Technology, 31/07/17. https://doi.org/10.23919/VLSIT.2017.7998151

 
2014 
A 42mW 230fs-Jitter Sub-sampling 60GHz PLL in 40nm CMOS

Szortyka, V, Shi, Q, Raczkowski, K, Parvais, B, Kuijk, M & Wambacq, P 2014, A 42mW 230fs-Jitter Sub-sampling 60GHz PLL in 40nm CMOS. in 2014 IEEE International Solid-State Circuits Conference. 2014 IEEE International Solid-State Circuits Conference, pp. 105-108, 2014 IEEE International Solid-State Circuits Conference, ISSCC, San Francisco, CA, United States, 9/02/14.

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies

Huynh Bao, T, Yakimets, D, Ryckaert, J, Ciofi, I, Baert, R, Veloso, A, Boemmels, J, Collaert, N, Roussel, P, Demuynck, S, Raghavan, P, Mercha, A, Tokei, Z, Verkest, D, Thean, AV-Y & Wambacq, P 2014, Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. in Solid State Device Research Conference (ESSDERC), 2014 44th European. IEEE, pp. 102-105, 44th European Solid State Device Research Conference (ESSDERC), Venice, Italy, 22/09/14. https://doi.org/10.1109/ESSDERC.2014.6948768

A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS

Spagnolo, A, Verbruggen, B, D'amico, S & Wambacq, P 2014, A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS. in European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th. IEEE, pp. 75-78, European Solid State Circuits Conference (ESSCIRC), Venice Lido, Italy, 22/09/14. https://doi.org/10.1109/ESSCIRC.2014.6942025

A 5th subharmonic, inverter-based injection locked oscillator with 72–83GHz locking range

Shi, Q, Wambacq, P, Guermandi, D & Giannini, V 2014, A 5th subharmonic, inverter-based injection locked oscillator with 72–83GHz locking range. in Radio Frequency Integrated Circuits Symposium, 2014 IEEE., RMO3C-4, pp. 185-188, 2014 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Tampa, FL, United States, 1/06/14. https://doi.org/10.1109/RFIC.2014.6851692

A 4.1mW 3.5GS/s 6b time interleaved ADC in 40nm CMOS

D'amico, S, Spagnolo, A, Donno, A, Chironi, V, Wambacq, P & Baschirotto, A 2014, 'A 4.1mW 3.5GS/s 6b time interleaved ADC in 40nm CMOS', IEEE Transactions on Microwave Theory and Techniques, vol. 62, no. 8, pp. 1724-1735.

A 4.1-mW 3.5-GS/s 6-Bit Time-Interleaved ADC in 40-nm CMOS

Spagnolo, A, Verbruggen, B, Wambacq, P & D'amico, S 2014, 'A 4.1-mW 3.5-GS/s 6-Bit Time-Interleaved ADC in 40-nm CMOS', IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, no. 7, pp. 466-470. https://doi.org/10.1109/TCSII.2014.2327340

 
2012 
A four-path 60 GHz phased-array receiver with injection-locked LO, hybrid beamforming and analog baseband section in 90 nm CMOS

Raczkowski, K, Mangraviti, G, Szortyka, V, Spagnolo, A, Parvais, B, Vandebriel, R, Vidojkovic, V, Soens, C, D'amico, S & Wambacq, P 2012, A four-path 60 GHz phased-array receiver with injection-locked LO, hybrid beamforming and analog baseband section in 90 nm CMOS. in 2012 IEEE Radio Frequency Integrated Circuits Symposium. 2012 IEEE Radio Frequency Integrated Circuits Symposium, pp. 431-434, 2012 IEEE Radio Frequency Integrated Circuits Symposium, Montreal, QC, Canada, 17/06/12.

 
2010 
A 2.6 mW 6b 2.2GS/S 4-times Interleaved Fully Dynamic Pipelined ADC in 40 nm Digital CMOS

Verbruggen, B, Craninckx, J, Kuijk, M, Wambacq, P & Van Der Plas, G 2010, A 2.6 mW 6b 2.2GS/S 4-times Interleaved Fully Dynamic Pipelined ADC in 40 nm Digital CMOS. in IEEE International Solid-State Circuits Conference (ISSCC). IEEE International Solid-State Circuits Conference (ISSCC), IEEE, pp. 296-297, Unknown, 7/02/10.

A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS

Verbruggen, B, Craninckx, J, Kuijk, M, Wambacq, P & Van Der Plas, G 2010, 'A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS', IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 45, pp. 2080-2090.

 
2009 
A Fully Integrated 7.3 kV HBM ESD-Protected Tranformer-Based 4.5-6 GHz CMOS LNA

Borremans, J, Thijs, S, Wambacq, P, Rolain, Y, Linten, D & Kuijk, M 2009, 'A Fully Integrated 7.3 kV HBM ESD-Protected Tranformer-Based 4.5-6 GHz CMOS LNA', IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 44, no. 2, pp. 344-353.

 
2008 
A Single-Inductor Dual-Band VCO in a 0.06mm2 5.6GHz Multi-Band Front-End in 90nm Digital CMOS

Borremans, J, Bevilacqua, A, Bronckers, S, Dehan, M, Kuijk, M, Wambacq, P & Craninckx, J 2008, A Single-Inductor Dual-Band VCO in a 0.06mm2 5.6GHz Multi-Band Front-End in 90nm Digital CMOS. in 2008 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). IEEE, 2008 IEEE International Solid-State Circuits Conference (ISSCC), San Fransisco, United States, 3/02/08.

 
 
OFDM-MIMO WLAN AP front-end gain and phase mismatch calibration

Liu, J, Bourdoux, A, Craninckx, J, Wambacq, P, Come, B, Donnay, S & Barel, A 2004, OFDM-MIMO WLAN AP front-end gain and phase mismatch calibration. in IEEE Radio and Wireless Conference (RAWCON 2004), Atlanta, GA, September 19-22, 2004. pp. 151-154, Unknown, 19/09/04.

Analog and RF circuits in 45 nm CMOS: planar bulk versus FinFET

Wambacq, P, Verbruggen, B, Scheir, K, Borremans, J, De Heyn, V, Van Der Plas, G, Mercha, A, Parvais, B, Subramanian, V, Jurzak, M, Decoutere, S & Donnay, S 2006, Analog and RF circuits in 45 nm CMOS: planar bulk versus FinFET. in Proceedings of ESSCIRC-ESSDIRC. Proceedings of ESSCIRC-ESSDIRC, pp. 54-57, Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet, Stockholm, Sweden, 21/09/09.

Analog and RF circuits in 45 nm CMOS and below: planar bulk versus FinFET

Wambacq, P, Verbruggen, B, Scheir, K, Borremans, J, De Heyn, V, Van Der Plas, G, Mercha, A, Parvais, B, Subramanian, V, Jurczak, M, Decoutere, S & Donnay, S 2006, Analog and RF circuits in 45 nm CMOS and below: planar bulk versus FinFET. in Proceedings of the 32nd European Solid-State Circuits Conference, Montreux, Switserland, September 19-21, 2006. pp. 54-57, Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet, Stockholm, Sweden, 21/09/09.

A CMOS IQ Direct Digital RF Modulator with Embedded RF FIR-Based Quantization Noise Filter

Gaber Mahdi Hussein, W, Wambacq, P, Craninckx, J & Ingels, M 2011, A CMOS IQ Direct Digital RF Modulator with Embedded RF FIR-Based Quantization Noise Filter. in IEEE European Solid-State Circuits Conference (ESSCIRC). IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 139-142, Unknown, 16/09/11.

A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter

Tsai, CH, Pepe, F, Mangraviti, G, Zong, Z, Craninckx, J & Wambacq, P 2019, A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter. in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference., 8902868, ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 111-114, 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019, Cracow, Poland, 23/09/19. https://doi.org/10.1109/ESSCIRC.2019.8902868

A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth

Renukaswamy, P, Markulic, N, Wambacq, P & Craninckx, J 2020, 'A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth', IEEE Journal of Solid - State Circuits, vol. 55, no. 12, 9197684, pp. 3294-3307. https://doi.org/10.1109/JSSC.2020.3021311